Vishal Gupta
Name: Vishal Gupta
Qualification: Ph.D
Designation: Research Scholar
Department: Electronic Engineering
Institute Name: University Of Rome, Tor Vergata
College Address: Via Del Politecnico 1 – 00133, Rome, Italy
Postal Address: House No. 82, Ward No. 15, Lahar, Bhind, Madhya Pradesh, India
Award For: Young Achiever Award
Publication Title: Journal
Paper Title: Investigation Of Hysteresis In Hole Transport Layer (Htl) - Free Metal Halide Perovskites Cells Under Dark Conditions
Journal Name: Nanotechnology
Volume: 31
Issue No.: Https://Doi.Org/10.1088/1361-6528/Aba713
Month Of Publication: October
Year: 2020
Page No.: 1-15
Issn: 1361-6528
About Vishal Gupta
Vishal Gupta is a Ph.D Research Scholar in the Department of Electronic Engineering at University of Rome, Tor Vergata, Italy since 2017, where he has been also associated with Defect & Fault Tolerance Group. Currently, he is working on various novel applications of resistive memory devices and circuit including fault analysis. He has completed Bachelor of Engineering in Electronics & Communication and Master of Technology in VLSI Design from India in 2012 and 2015, respectively. Previously, he was also associated with Chartered Institute of Technology, Abu Road, Rajasthan, India as an assistant professor for 3 years (during 2012-2013 and 2015-2017). He has also published various articles in peer-reviewed Journals including Scopus and web of science and various International Conferences. He has been awarded Best Paper Award in Design & Technology of Integrated Circuit (DTIS) 2019, Young Scientist award & Young Scientist Fellowship award by M.P. Council of Science and Technology, Government of Madhya Pradesh, India in 2016. He is also associated various technical societies including IEEE, HiPEAC, IAAM, ISCA Govt. of India, IAENG. His principal research interest lies in the field of Device characterization and modelling, Design issues in Nanotechnology (Memristors, FinFET, CMOS), VLSI design and design for testability (Analog & Digital), Fault-tolerant design techniques manufacturing defects, Process variation & yield characterization.